1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a pulse signal generation circuit for receiving a pulse signal of a predefined pulse width and generating a pulse signal of a desired pulse width by adjusting the pulse width.
2. Description of the Related Art
In general, semiconductor devices, such as a double data rate (DDR) synchronous DRAM (SDRAM), include a variety of internal circuits for several internal operations. Among the internal circuits, a pulse signal generation circuit generates a pulse signal of a desired pulse width. The pulse signal generated from the pulse signal generation circuit is used for sampling a clock signal during a desired period or enabling a specific circuit during a desired period.
FIG. 1 is a circuit diagram of a conventional pulse signal generation circuit.
Referring to FIG. 1, the pulse signal generation circuit includes a signal delay unit 110 and a pulse output unit 120.
The signal delay unit 110 is configured to delay an input pulse signal IN by a predefined time and includes a plurality of inverters. The signal delay unit 110 includes even number (2n) of inverters (where n is a natural number). The pulse output unit 120 outputs an output pulse signal OUT in response to an input pulse signal IN and an output signal of the signal delay unit 110.
FIG. 2 is a waveform diagram explaining the operation of the pulse signal generation circuit illustrated in FIG. 1. For illustration purposes, the input pulse signal IN having a logic-low pulse duration is taken as an example.
Referring to FIGS. 1 and 2, the input pulse signal IN is inputted to the signal delay unit 110 and the pulse output unit 120. The output pulse signal OUT changes from a logic high level to a logic low level in response to the input pulse signal IN changing from a logic high level to a logic low level. The signal delay unit 110 includes even number of inverters. A first inverter INV1 inverts and delays the input pulse signal IN and output a delayed signal D_INV1, and a second inverter INV2 inverts and delays the output signal D_INV1 of the first inverter INV1 and outputs a delayed signal D_INV2. The pulse output unit 120 generates the output pulse signal OUT in response to the input pulse signal IN and the output signal D_INV2n of the signal delay unit 110. The output pulse signal OUT changes from a logic low level to a logic high level in response to a change of the output signal D_INV2n from a logic low level to a logic high level.
Consequently, the output pulse signal OUT has a pulse width corresponding to the delay time of the signal delay unit 110.
Meanwhile, as described above with reference to FIGS. 1 and 2, the input pulse signal IN is inputted to the signal delay unit 110 and is delayed by the predefined time. At this time, the signal delay unit 110 includes a plurality of inverters INV1, INV2, . . . INV2n. 
Here, the signal delay unit 110 inverts and delays the input pulse signal IN. Such an operation may cause various malfunctions such as a coupling of peripheral circuits, and consumes a relatively large amount of power. In addition, as a larger number of inverters are provided in order to further widen the pulse width of the output pulse signal OUT, the above-mentioned features become more significant and the layout size further increases. Moreover, interconnection wirings become more complicated.